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m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 1 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. based on ddr 3 - 1066 /1333 /1600 128 mx 16 (1gb) / 256 mx8 (2gb) / 256 mx8 (4gb) sdram b - die features ?performance: speed sort pc 3 - 8500 pc 3 - 10600 pc 3 - 1 2800 unit - be - cg - d i dimm cas latency 7 9 1 1 fck C C C ? 20 4 - pin small outline dual in - line memory module (so - dimm) ? 1gb: 128 mx64 unbuffered ddr 3 s o - dimm based on 128 mx16 ddr 3 sdram b - die devices . ? 2gb: 256mx64 unbuffered ddr3 s o - dimm based on 256mx8 ddr 3 sdram b - die devices . ? 4gb: 512 mx64 unbuffered ddr3 s o - dimm based on 256 mx 8 ddr 3 sdram b - die devices . ? intended for 533 mhz /667mhz /800mhz applications ? inputs and outputs are sstl - 1 5 compatible ? v dd = v ddq = 1. 5 v ? 0.075 v ? sdrams have 8 int ernal banks for concurrent operation ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs transitions with clock t ransitions. ? address and control signals are fully synchronous to positive clock edge ? programmable operation: - dimm ??? latency : 5, 6, 7, 8 /pc3 - 8500; 5, 6 , 7, 8, 9 /pc3 - 10600 ; 5, 6 , 7, 8, 9 , 10 , 11 /pc3 - 12800 - burst type: sequential or interleave - burst length: bc 4, bl 8 - operation: burst read and write ? two different termination values (rtt_nom & rtt_wr) ? 1 4 /10/ 1 (r ow/column/rank) addressing for 1gb ? 1 5 /10/ 1 (row/column/rank) addressing for 2gb ? 15/10/ 2 (row/column/rank) addressing for 4 gb ? extended operating temperature rage ? auto self - refresh option ? serial presence detect ? gold contacts ? 1gb: sdrams are in 96 - ball bga package ? 2gb: sdrams are in 78 - ball bga package ? 4 gb: sdrams are in 78 - ball bga package ? rohs complian ce and halogen f ree description m 2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N are un - buffe r ed 20 4 - pin double data rate 3 (ddr 3 ) synchr onous dram small outline dual in - line memory module ( so - dimm), organized as one rank of 128m x64 ( 1g b) and one rank of 256mx64 (2gb) / 512mx64 (4gb) high - speed memory array. modules use four 128 mx16 ( 1g b ) 96 - ball bga packaged devices and eight 256 mx 8 (2gb) 78 - ball bga packaged devices and sixteen 256 mx8 ( 4 gb) 78 - ball bga packaged devices . these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation betw een suppliers. all elixir ddr 3 so dimms provide a high - performance, flexible 8 - byte interface in a space - saving footprint. the dimm is intended for use in applications operating of 533 mhz /667mhz /800mhz clock speeds and achieves high - speed data transfer rate s of 1066 mbps / 1 333mbps /1600mbps . prior to any access operation, the device ??? latency and burst /length/operation type must be programmed into the dimm by address inputs a0 - a1 3 (1gb)/a0 - a1 4 ( 2gb/ 4 gb) and i/o inputs ba0~ ba 2 using the mode register set cycle. the dimm uses serial presence - detect implemented via a serial eeprom usin g a standard iic protocol . the first 128 bytes of s pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer.
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 2 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ordering information part number speed organization power leads note m2s1g64c bh4b5p - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ cl = 7 ) 128mx64 1. 5 v gold m2s1g64cbh4b5p - cg ddr 3 - 1 333 pc 3 - 10600 667mhz ( 1.5ns @ cl = 9) m2s1g64cbh4b5p - d i ddr3 - 1600 pc3 - 12800 800mhz(1.25ns @ cl=1 1 ) m2s2g64cb88b5n - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.8 75ns @ cl = 7 ) 256 mx64 m2s2g64cb88b5n - cg ddr 3 - 1 333 pc 3 - 10600 667mhz ( 1.5ns @ cl = 9) m2s2g64cb88b5n - d i ddr3 - 1600 pc3 - 12800 800mhz(1.25ns @ cl=11 ) M2S4G64CB8HB5N - be ddr 3 - 1066 pc 3 - 85 00 533 mhz ( 1.875ns @ cl = 7 ) 512mx64 M2S4G64CB8HB5N - cg ddr 3 - 1 333 pc 3 - 10600 667mhz ( 1.5ns @ cl = 9) M2S4G64CB8HB5N - d i ddr3 - 1600 pc3 - 12800 800mhz(1.25ns @ cl=11 ) pin description pin name description pin name description ck0 , ck1 clock inputs, positive line dq0 - dq63 data input/output ??? , ??? clock inputs, negative line dqs0 - dqs7 d ata strobes cke0 , cke1 clock enable ???? - ???? data strobes complement ??? row address strobe dm0 - dm7 data masks ??? column address strobe ????? ? temperature event pin ?? write enable ????? ? reset pin ?? , ? ? chip selects v ref dq , v ref ca input/output reference a0 - a9, a1 1 , a13 - a15 address inputs v ddspd spd and temp sensor power a10/ap address input/auto - p recharge sa0, sa1 serial presence detect address inputs a1 2 / ?? address input/ burst chop vtt termination voltage ba0 - ba2 sdram bank address inputs v ss ground odt0, odt1 active termination control lines v dd core and i/o power scl serial presence detect clock input nc no connect sda serial presence detect data input/output note: a1 4 is for 2gb and 4 gb m odules only.
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 3 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ddr 3 sdram pin assignment pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref dq 2 v ss 53 dq 19 54 v ss 105 v dd 106 v dd 155 v ss 156 v ss 3 v ss 4 dq 4 55 v ss 56 dq2 8 107 a10/ap 108 ba1 157 dq4 2 158 dq4 6 5 dq 0 6 dq 5 57 dq 24 58 dq2 9 109 ba0 110 ??? ? 159 dq43 160 dq47 7 dq 1 8 v ss 59 dq 25 60 v ss 111 v dd 112 v dd 161 v ss 162 v ss 9 v ss 10 ???? ? 61 v ss 62 ???? ? 113 ?? ? 114 ?? ? 163 dq4 8 164 dq5 2 11 dm0 12 dqs0 63 dm3 64 dqs3 115 ??? 116 odt0 165 dq49 166 dq53 13 v ss 14 v ss 65 v ss 66 v ss 117 v dd 118 v dd 167 v ss 168 v ss 15 dq2 16 dq 6 67 dq26 68 dq30 119 a13 /nc 120 odt1 169 ???? ? 170 dm6 17 dq 3 18 dq7 69 dq27 70 dq31 121 ?? ? 122 nc 171 dqs6 172 v ss 19 v ss 20 v ss 71 v ss 72 v ss 123 v dd 124 v dd 173 v ss 174 dq54 21 dq8 22 dq1 2 73 cke0 74 cke1 125 nc 126 v refca 175 dq50 176 dq55 23 dq9 24 dq13 75 v dd 76 v dd 127 v ss 128 v ss 177 dq51 178 v ss 25 v ss 26 v ss 77 nc 78 a15/ nc 129 dq3 2 130 dq3 6 179 v ss 180 dq60 27 ???? ? 28 dm1 79 ba2 80 a14/ nc 131 dq33 132 dq37 181 dq56 182 dq 61 29 dqs1 30 ????? ? 81 v dd 82 v dd 133 v ss 134 v ss 183 dq57 184 v ss 31 v ss 32 v ss 83 a12/ ?? 84 a11 135 ???? ? 136 dm4 185 v ss 186 ???? ? 33 dq10 34 dq14 85 a9 86 a7 137 dqs4 138 v ss 187 dm7 188 dqs7 35 dq11 36 dq15 87 v dd 88 v dd 139 v ss 140 dq3 8 189 v ss 190 v ss 37 v ss 38 v ss 89 a8 90 a6 141 dq3 4 142 dq39 191 dq58 192 dq62 39 dq16 40 dq20 91 a5 92 a4 143 dq35 144 v ss 193 dq59 194 dq63 41 dq17 42 dq21 93 v dd 94 v dd 145 v ss 146 dq4 4 195 v ss 196 v ss 43 v ss 44 v ss 95 a3 96 a2 147 dq4 0 148 dq45 197 sa0 198 ??? ?? ? 45 ???? 46 dm2 97 a 1 98 a0 149 dq41 150 v ss 199 v ddspd 200 sda 47 dqs2 48 v ss 99 v dd 100 v dd 151 v ss 152 ???? ? 201 sa1 202 scl 49 v ss 50 dq22 101 ck0 102 ck1 153 dm5 154 dqs5 203 vtt 204 vtt 51 dq18 52 dq23 103 ??? ? 104 ?? ? ? note: a1 4 is for 2 gb and 4 gb modules only.
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 4 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. input / output functional description symbol type polarity function ck0 , ck1 ??? , ??? input cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of c k and falling edge of ?? . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke0 , cke1 input active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. ?? , ?? input active low enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the co mmand decoder is disabled, new commands are ignored but previous operations continue, rank 0 is selected by ?? ; rank 1 is selected by ?? ? ??? , ??? , ?? input active low when sampled at the positive rising edge of ck and falling edge of ?? , signals ??? , ??? , ?? define the operation to be executed by the sdram. odt0, odt1 input active high asserts on - die termination for dq, dm, dqs, and ??? signals if enabled via the ddr3 sdram mode register. dm0 C dm 7 input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dq s 0 C dq s7 ???? C ???? i/o cross point the data strobes, ass ociated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdram and is sent at the leading edge of the data window. ??? signals are complements, and timing is relative to the cross point of respective dqs and ??? . if the module is to be operated in single ended strobe mode, all ??? signals must be tied on the system board to v ss and ddr3 sdram mode registers programmed appropriately. ba0, ba1, ba2 input - selects which ddr3 sdram internal bank of four or eight is activated. a0 C a9 a10/ap a1 1 a12 / ?? ? a13 C a15 input - during a bank activate command cycle, defines the row address when sampled at the cross point of the ri sing edge of ck and falling edge of ?? . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ?? . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0 - ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0 - ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 - b a n inputs. if ap is low, then ba0 - b a n are used to define which bank to precharge. dq0 C dq 63 input - data input/output pins. v dd , v ddspd , v ss supply - power supplies for core, i/o, serial presence detect, temp sensor, and ground for the module. v ref dq, v ref ca supply - reference voltage for sstl15 inputs sda i/o - this is a bidirectional pin used to transfer data into or out of the spd eep rom and temp sensor. a resistor must be connected from the sda bus line to v ddspd on the system planar to act as a pull up. scl input - this signal is used to clock data into and out of the spd eeprom and temp sensor. sa0 C sa2 input - address pins used to select the serial presence detect and temp sensor base address. ????? ? out put - the ????? pin is reserved for use to flag critical module temperature. ????? ? in put - this signal resets the ddr3 sdram zq supply - reference pin for zq calibration
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 5 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. functional block diagram [1g b C 1 r ank, 128 mx16 ddr 3 sdrams ] n o t e s : 1 . d q w i r i n g m a y d i f f e r f r o m t h a t s h o w n h o w e v e r , d q , d m , d q s , a n d ? ? ? ? r e l a t i o n s h i p s a r e m a i n t a i n e d a s s h o w n . s p d s c l w p s c l s d a s a 0 s a 1 a 0 a 1 a 2 v t t v r e f d q v r e f c a v d d v d d s p d v t t s p d d 0 - d 7 d 0 - d 7 v s s d 0 - d 7 d 0 - d 7 , s p d c k 0 ? ? ? c k 1 ? ? ? ? ? ? ? ? d 0 - d 3 d 0 - d 3 d 0 - d 7 d 4 - d 7 d 4 - d 7 d q s 0 ? ? ? ? d m 0 d q s 1 d m 1 ? ? ? ? l d q s l ? ? ? u d m ? ? ? ? u d q s l d m d 0 ? ? ? ? ? ? ? ? ? ? c k 0 ? ? ? c k e 0 o d t 0 a [ 0 : 1 3 ] / b a [ 0 : 2 ] z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 0 : 1 3 ] / b a [ 0 : 2 ] d q s 2 ? ? ? ? d m 2 d q s 3 d m 3 ? ? ? ? l d q s l ? ? ? u d m ? ? ? ? u d q s l d m d 1 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 0 : 1 3 ] / b a [ 0 : 2 ] d q s 4 ? ? ? ? d m 4 d q s 5 d m 5 ? ? ? ? l d q s l ? ? ? u d m ? ? ? ? u d q s l d m d 2 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 0 : 1 3 ] / b a [ 0 : 2 ] d q s 6 ? ? ? ? d m 6 d q s 7 d m 7 ? ? ? ? l d q s l ? ? ? u d m ? ? ? ? u d q s l d m d 3 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 0 : 1 3 ] / b a [ 0 : 2 ] v t t v d d v t t d q [ 0 : 1 5 ] d q [ 0 : 1 5 ] d q [ 0 : 1 5 ] d q [ 0 : 1 5 ] d q [ 0 : 1 5 ] d q [ 1 6 : 3 1 ] d q [ 3 2 : 4 7 ] d q [ 4 8 : 6 3 ]
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 6 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. functional block diagram [2g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 i / o 0 d 0 n o t e s : 1 . d q - t o - i / o w i r i n g i s s h o w n a s r e c o m m e n d e d b u t m a y b e c h a n g e d . 2 . d q / d q s / d q s / o d t / d m / c k e / s r e l a t i o n s h i p s m u s t b e m a i n t a i n e d a s s h o w n . 3 . f o r e a c h d r a m , a u n i q u e z q r e s i s t o r i s c o n n e c t e d t o g r o u n d . t h e z q r e s i s t o r i s 2 4 0 ? 1 % . 4 . o n e s p d e x i s t s p e r m o d u l e . z q v d d s p d v s s v r e f d q v r e f c a v d d / v d d q s p d d 0 - d 7 d 0 - d 7 d 0 - d 7 b a 0 - b a 2 d 0 - d 7 b a 0 - b a 2 : s d r a m s d 0 - d 7 a 0 - a 1 4 ? ? ? ? ? ? c k e 0 ? ? o d t 0 a 0 - a 1 4 : s d r a m s d 0 - d 7 ? ? ? : s d r a m s d 0 - d 7 ? ? : s d r a m s d 0 - d 7 o d t : s d r a m s d 0 - d 7 ? ? ? : s d r a m s d 0 - d 7 c k e : s d r a m s d 0 - d 7 i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 i / o 0 d 4 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 0 d q s 0 ? ? ? ? d m 4 d q s 4 ? ? ? ? ? ? d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 i / o 0 d 1 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 1 d q s 1 ? ? ? ? d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 i / o 0 d 5 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 5 d q s 5 ? ? ? ? d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 i / o 0 d 2 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 2 d q s 2 ? ? ? ? d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 i / o 0 d 6 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 6 d q s 6 ? ? ? ? d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 i / o 0 d 3 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 3 d q s 3 ? ? ? ? d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 i / o 0 d 7 z q i / o 1 i / o 2 i / o 3 i / o 4 i / o 5 i / o 6 i / o 7 d m ? ? d q s ? ? ? d m 7 d q s 7 ? ? ? ? c k 0 c k : s d r a m s d 0 - d 7 ? ? ? ? ? : s d r a m s d 0 - d 7 ? ? ? ? ? ? ? ? ? ? : s d r a m s d 0 - d 7 d d r 3 s d r a m v t t c k e 0 , a [ 1 4 : 0 ] , ? ? ? , ? ? ? , ? ? , o d t 0 , b a [ 2 : 0 ] , ? ? d d r 3 s d r a m v d d c k ? ? s p d s c l w p s c l s d a s a 0 s a 1 a 0 a 1 a 2
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 7 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. functional block diagram [4g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] d q s 3 ? ? ? ? d m 3 d q [ 2 4 : 3 1 ] d q s ? ? ? d q [ 0 : 7 ] d m d 1 1 n o t e s : 1 . d q w i r i n g m a y d i f f e r f r o m t h a t s h o w n h o w e v e r , d q , d m , d q s , a n d ? ? ? ? r e l a t i o n s h i p s a r e m a i n t a i n e d a s s h o w n . ? ? ? ? ? ? ? ? ? ? c k 1 ? ? ? c k e 1 o d t 1 a [ 0 : 1 4 ] / b a [ 0 : 2 ] z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t a [ 0 : 1 4 ] / b a [ 0 : 2 ] d q s 1 ? ? ? ? d m 1 d q [ 8 : 1 5 ] d q s 0 ? ? ? ? d m 0 d q [ 0 : 7 ] d q s 2 ? ? ? ? d m 2 d q [ 1 6 : 2 3 ] s p d s c l w p s c l s d a s a 0 s a 1 a 0 a 1 a 2 v t t v r e f d q v r e f c a v d d v d d s p d v t t s p d d 0 - d 1 5 d 0 - d 1 5 v s s d 0 - d 1 5 d 0 - d 1 5 , s p d c k 0 ? ? ? c k 1 ? ? ? ? ? ? ? ? d 0 - d 7 d 0 - d 7 d 0 - d 1 5 d 8 - d 1 5 d 8 - d 1 5 d q s ? ? ? d q [ 0 : 7 ] d m d 1 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 0 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 2 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 3 ? ? c k 0 ? ? ? c k e 0 o d t 0 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 9 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 8 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 1 0 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 4 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 1 4 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 1 5 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 1 3 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 1 2 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 6 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 7 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s ? ? ? d q [ 0 : 7 ] d m d 5 z q 2 4 0 o h m + / - 1 % ? ? ? ? ? ? ? ? ? ? c k ? ? c k e o d t d q s 4 ? ? ? ? d m 4 d q [ 3 2 : 3 9 ] d q s 6 ? ? ? ? d m 6 d q [ 4 8 : 5 5 ] d q s 7 ? ? ? ? d m 7 d q [ 5 6 : 6 3 ] d q s 5 ? ? ? ? d m 5 d q [ 4 0 : 4 7 ] v d d v t t c t e r m v t t v d d c t e r m v t t c k e 0 c k e 1 ? ? ? ? d 0 - d 7 d 8 - d 1 5 d 0 - d 7 d 8 - d 1 5 o d t 0 o d t 1 d 0 - d 7 d 8 - d 1 5 a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ] a [ 0 : 1 4 ] / b a [ 0 : 2 ]
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 8 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. serial presence detect [1gb C 1 rank, 128 mx16 ddr3 sdrams] byte description spd data entry (hex.) - be - cg - d i 0 crc range, eeprom bytes, bytes used 92 92 92 1 spd revision 10 10 10 2 dram device type 0b 0b 0b 3 module type ( form factor) 03 03 03 4 sdram device density and banks 03 03 03 5 sdram device row and column count 11 11 11 6 reserved 00 00 00 7 module ranks and device dq count 02 02 02 8 ecc tag and module memory bus width 03 03 03 9 fine timebase dividend/divis or (in ps) 52 52 52 10 medium timebase dividend 01 01 01 11 medium timebase divisor 08 08 08 12 minimum sdram cycle time (tckmin) 0f 0c 0a 13 reserved 00 00 00 14 cas latencies supported 1 e 3 e f e 15 cas latencies supported 00 00 00 16 minimum cas la tency time (taamin) 69 69 69 17 minimum write recovery time (twrmin) 78 78 78 18 minimum cas - to - cas delay (trcdmin) 69 69 69 19 minimum row active to row active delay (trrdmin) 50 3c 3c 20 minimum row precharge delay (trpmin) 69 69 69 21 upper nibble for tras and trc 11 11 11 22 minimum active - to - precharge delay (trasmin) 2c 20 18 23 minimum active - to - active/refresh delay (trcmin) 95 89 81 24 minimum refresh recovery delay (trfcmin) lsb 00 00 00 25 minimum refresh recovery delay (trfcmin) msb 05 05 05 26 minimum internal write - to - read command delay (twtrmin) 3c 3c 3c 27 minimum internal read - to - precharge command delay (trtpmin) 3c 3c 3c 28 minimum four active window delay (tfawmin) lsb 01 01 01 29 minimum four active window delay (tfawmin) msb 9 0 68 40 30 sdram device output drivers sup p orted 83 83 83 31 sdram device thermal and refresh options 05 05 05 32 module thermal sensor 00 00 00 33 sdram device type 00 00 00 60 module height (nominal) 0f 0f 0f 61 module thickness (max) 01 01 01 62 raw card id reference 22 22 22 63 dram address mapping edge connector 00 00 00 117 module manufacture id 83 83 83 118 module manufacture id 0b 0b 0b 119 - 121 module manufacturer information -- -- -- 126 crc -- -- -- 12 7 crc -- -- -- 128 - 145 module pa rt number -- -- -- 146 module die revision -- -- -- 147 module pcb revision -- -- -- 150 - 175 manufacturer reserved -- -- -- 176 - 255 customer reserved -- -- --
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 9 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. serial presence detect [2gb C 1 rank , 256 mx 8 ddr3 sdrams] byte description seria l pd data entry (hex.) - be - cg - d i 0 crc range, eeprom bytes, bytes used 92 92 92 1 spd revision 10 10 10 2 dram device type 0b 0b 0b 3 module type (form factor) 03 03 03 4 sdram device density and banks 03 03 03 5 sdram device row and column coun t 19 19 19 6 reserved 00 00 00 7 module ranks and device dq count 01 01 01 8 ecc tag and module memory bus width 03 03 03 9 fine timebase dividend/divisor (in ps) 52 52 52 10 medium timebase dividend 01 01 01 11 medium timebase divisor 08 08 08 12 m inimum sdram cycle time (tckmin) 0f 0c 0a 13 reserved 00 00 00 14 cas latencies supported 1 e 3 e f e 15 cas latencies supported 00 00 00 16 minimum cas latency time (taamin) 69 69 69 17 minimum write recovery time (twrmin) 78 78 78 18 minimum cas - to - ca s delay (trcdmin) 69 69 69 19 minimum row active to row active delay (trrdmin) 3c 30 30 20 minimum row precharge delay (trpmin) 69 69 69 21 upper nibble for tras and trc 11 11 11 22 minimum active - to - precharge delay (trasmin) 2c 20 18 23 minimum activ e - to - active/refresh delay (trcmin) 95 89 81 24 minimum refresh recovery delay (trfcmin) lsb 00 00 00 25 minimum refresh recovery delay (trfcmin) msb 05 05 05 26 minimum internal write - to - read command delay (twtrmin) 3c 3c 3c 27 minimum internal read - to - precharge command delay (trtpmin) 3c 3c 3c 28 minimum four active window delay (tfawmin) lsb 01 00 00 29 minimum four active window delay (tfawmin) msb 2c f0 f0 30 sdram device output drivers suported 83 83 83 31 sdram device thermal and refresh optio ns 05 05 05 32 module thermal sensor 00 00 00 33 sdram device type 00 00 00 60 module height (nominal) 0f 0f 0f 61 module thickness (max) 11 11 11 62 raw card id reference 41 41 41 63 dram address mapping edge connector 00 00 00 117 module manufactu re id 83 83 83 118 module manufacture id 0b 0b 0b 119 - 121 module manufacturer information -- -- -- 126 crc -- -- -- 127 crc -- -- -- 128 - 145 module part number -- -- -- 146 module die revision -- -- -- 147 module pcb revision -- -- -- 150 - 175 manuf acturer reserved -- -- -- 176 - 255 customer reserved -- -- --
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 10 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. serial presence detect [4gb C 2 ranks, 256mx8 ddr3 sdrams] byte description serial pd data entry (hex.) - be - cg - d i 0 crc range, eeprom bytes, bytes used 92 92 92 1 spd revision 10 10 10 2 dram device type 0b 0b 0b 3 module type (form factor) 03 03 03 4 sdram device density and banks 03 03 03 5 sdram device row and column count 19 19 19 6 reserved 00 00 00 7 module ranks and device dq count 09 09 09 8 ecc tag and module me mory bus width 03 03 03 9 fine timebase dividend/divisor (in ps) 52 52 52 10 medium timebase dividend 01 01 01 11 medium timebase divisor 08 08 08 12 minimum sdram cycle time (tckmin) 0f 0c 0a 13 reserved 00 00 00 14 cas latencies supported 1 e 3 e f e 15 cas latencies supported 00 00 00 16 minimum cas latency time (taamin) 69 69 69 17 minimum write recovery time (twrmin) 78 78 78 18 minimum cas - to - cas delay (trcdmin) 69 69 69 19 minimum row active to row active delay (trrdmin) 3c 30 30 20 minimum row precharge delay (trpmin) 69 69 69 21 upper nibble for tras and trc 11 11 11 22 minimum active - to - precharge delay (trasmin) 2c 20 18 23 minimum active - to - active/refresh delay (trcmin) 95 89 81 24 minimum refresh recovery delay (trfcmin) lsb 00 00 00 25 minimum refresh recovery delay (trfcmin) msb 05 05 05 26 minimum internal write - to - read command delay (twtrmin) 3c 3c 3c 27 minimum internal read - to - precharge command delay (trtpmin) 3c 3c 3c 28 minimum four active window delay (tfawmin) lsb 01 00 00 29 minimum four active window delay (tfawmin) msb 2c f0 f0 30 sdram device output drivers suported 83 83 83 31 sdram device thermal and refresh options 05 05 05 32 module thermal sensor 00 00 00 33 sdram device type 00 00 00 60 module height (nomi nal) 0f 0f 0f 61 module thickness (max) 11 11 11 62 raw card id reference 45 45 45 63 dram address mapping edge connector 00 00 00 117 module manufacture id 83 83 83 118 module manufacture id 0b 0b 0b 119 - 121 module manufacturer information -- -- -- 126 crc -- -- -- 127 crc -- -- -- 128 - 145 module part number -- -- -- 146 module die revision -- -- -- 147 module pcb revision -- -- -- 150 - 175 manufacturer reserved -- -- -- 176 - 255 customer reserved -- -- --
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 11 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. environmental requirements s ymbol parameter rating units t opr operating temperature (ambient) 0 to 85 c t stg storage temperature - 5 5 to + 1 0 0 c note : stress greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functiona l op eration at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended peri ods may affect reliability . absolute maximum dc ratings symbol parameter rating units note v dd voltage on vdd pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v dd q voltage on vddq pins relative to vss - 0.4 v ~ 1.975 v v 1, 3 v in , v out voltage on i/o pins relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature - 5 5 to +1 0 0 c 1, 2 note : 1. stresses greater than those listed un der absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect reliability 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51 - 2 standard. 3 . vdd and vddq must be within 300 mv of each other at all times;and vref must be not greater operating temperature conditions symbol parameter rating units note t op e r normal operating temperature range 0 to 85 c 1, 2 extended temperature range 85 to 95 c 1, 3 note: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51 - 2. 2. the normal temperature range specifies the temperatures wher e all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 to 85 c under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85 c and 95 c case temperature. full specifications are supported in this range, but the following additional conditions apply: a ) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extended temperature range. please refer to supplier data sheet and/ or the dimm spd for option availability. b ) if self - refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self - refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self - refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). please refer to the supplier data sheet and/or the dimm spd for auto self - refresh option availability, extended temperature range support and trefi requirements in the extended temp erature range. dc electrical characteristics and operating conditions symbol parameter min typ max units notes v dd supply voltage 1.425 1.5 1.575 v 1,2 v dd q output supply voltage 1.425 1.5 1.575 v 1,2 note: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together.
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 12 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. single - ended ac and dc input levels for command and address symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) ddr3 - 1600( - d i ) units note min. max. min. max. min. max. v ih.ca(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd vref + 0.100 vdd v 1 v il.ca(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 vss vref - 0.100 v 1 v ih.ca(ac) ac input logic high vref + 0.175 note 2 vref + 0.175 note 2 vref + 0.175 note 2 v 1, 2 v il.ca(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0.175 note 2 vref - 0.175 v 1, 2 v ih.ca(ac150) ac input logic high vref + 0.15 note 2 vref + 0.15 note 2 vref + 0.15 note 2 v 1, 2 v il.ca(ac150) a c input logic low note 2 vref - 0.15 note 2 vref - 0.15 note 2 vref - 0.15 v 1, 2 v ref ca (dc) reference voltage for add, cmd inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3, 4 note: 1. for input only pins except reset#. vref = vrefca(dc). 2. s ee overshoot and unders hoot specifications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/2 +/ - 15 mv. single - ended ac and dc input levels for dq and dm symbol parameter ddr3 - 1066 ( - be) ddr3 - 1333 ( - cg) ddr3 - 1600( - d i ) units note min. max. min. max. min. max. v ih.dq(dc) dc input logic high vref + 0.100 vdd vref + 0.100 vdd vref + 0.100 vdd v 1 v il.dq(dc) dc input logic low vss vref - 0.100 vss vref - 0.100 vss vref - 0.100 v 1 v ih.dq(ac) ac input logic high vref + 0.175 note 2 vref + 0.15 note 2 vref + 0.15 note 2 v 1, 2, 5 v il.dq(ac) ac input logic low note 2 vref - 0.175 note 2 vref - 0. 15 note 2 vref - 0.15 v 1, 2, 5 v refdq(dc) reference voltage for dq, dm inputs 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd 0.49 x vdd 0.51 x vdd v 3, 4 note: 1. for input only pins except reset#. vref = vrefdq(dc). 2. s ee overshoot and unders hoot speci fications in the device datasheet . 3. the ac peak noise on vref may not allow vref to deviate from vrefdq(dc) by more than +/ - 1% vdd (for reference: approx. +/ - 15 mv). 4. for reference: approx. vdd/2 +/ - 15 mv. 5. single - ended swing requirement for dqs, dqs# is 350 mv (peak to peak). differential swing requirement for dqs - dqs# is 700 mv (peak to peak).
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 13 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1. 5v 0.075 v [1g b C 1 r ank, 128 mx 16 ddr 3 sdrams ] symbol parame ter/condition pc3 - 8500 pc3 - 10600 pc3 - 1 2800 unit ( - be) ( - cg) ( - d i ) idd0 operating one bank active - precharge current 396 440 484 ma idd1 operating one bank active - read - precharge current 550 572 594 ma idd2p0 precharge power - down current slow exi t 53 53 53 ma idd2p1 precharge power - down current fast exit 132 154 176 ma idd2q precharge quiet standby current 132 154 176 ma idd2n precharge standby current 141 163 185 ma idd3p active power - down current 154 176 198 ma idd3n active s tandby current 132 176 198 ma idd4r operating burst read current 880 1078 1188 ma idd4w operating burst write current 924 1122 1232 ma idd5b burst refresh current 836 880 946 ma idd6 self refresh current: normal temperature range 53 53 5 3 ma idd7 operating bank interleave read current 1650 1870 2090 ma t case = 0 c ~ 85 c; v ddq = v dd = 1. 5 v 0. 075 v [2g b C 1 r ank, 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 pc3 - 1 2800 unit ( - be) ( - cg) ( - di ) idd0 operating one bank active - precharge current 660 748 836 ma idd1 operating one bank active - read - precharge current 836 880 924 ma idd2p0 precharge power - down current slow exit 106 106 106 ma idd2p1 precharge power - down current fast exit 220 264 308 ma idd 2q precharge quiet standby current 264 308 352 ma idd2n precharge standby current 282 326 370 ma idd3p active power - down current 264 308 352 ma idd3n active standby current 264 352 396 ma idd4r operating burst read current 1232 1452 1584 ma idd4w operating burst write current 1276 1452 1628 ma idd5b burst refresh current 1672 1760 1892 ma idd6 self refresh current: normal temperature range 106 106 106 ma idd7 operating bank interleave read current 2948 3388 3828 ma t case = 0 c ~ 85 c; v ddq = v dd = 1. 5 v 0. 075 v [4 g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] symbol parameter/condition pc3 - 8500 pc3 - 10600 pc3 - 1 2800 unit ( - be) ( - cg) ( - d i ) idd0 operating one bank active - precharge current 942 1074 1206 ma idd1 operating one bank active - read - precharge current 1118 1206 1294 ma idd2p0 precharge power - down current slow exit 211 211 211 ma idd2p1 precharge power - down current fast exit 440 528 616 ma idd2q precharge quiet standby current 528 616 704 ma idd2n precharge standby curr ent 563 651 739 ma idd3p active power - down current 528 616 704 ma idd3n active standby current 546 678 766 ma idd4r operating burst read current 1514 1778 1954 ma idd4w operating burst write current 1558 1778 1998 ma idd5b burst refresh curre nt 1954 2086 2262 ma idd6 self refresh current: normal temperature range 211 211 211 ma idd7 operating bank interleave read current 3230 3714 4198 ma
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 14 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. standard speed bins ddr3 - 1066 mhz speed bin ddr3 - 1066 unit cl - nrcd - nrp 7 - 7 - 7 ( - be) 8 - 8 - 8 ( - bf) parameter symbol min max min max. internal read command to first data taa 13.125 20.000 15.000 20.000 ns act to internal read or write delay time trcd 13.125 - 15.000 - ns pre command period trp 13.125 - 15.000 - ns act to act or ref c ommand period trc 50.625 - 52.500 - ns act to pre command period tras 37.500 9*trefi 37.500 9*trefi ns cl=5 cwl=5 tck(avg) 3.000 3.300 3.000 3.300 ns cwl=6 tck(avg) reserved reserved ns cl=6 cwl=5 tck(avg) 2.500 3.300 2.500 3.300 ns cwl=6 tck(avg) reserved reserved ns cl=7 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 reserved ns cl=8 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns supported cl settings 5, 6,7,8 6,8 nck supported cwl se ttings 5,6 5,6 nck ddr3 - 1333mhz speed bin ddr3 - 1333 unit cl - nrcd - nrp 8 - 8 - 8 ( - cf) 9 - 9 - 9 ( - cg) parameter symbol min max min max internal read command to first data taa 12.000 20.000 13. 125 (13.125) 5,11 20.000 ns act to internal read or write delay time tr cd 12.000 - 13. 125 (13.125) 5,11 - ns pre command period trp 12.000 - 13. 125 (13.125) 5,11 - ns act to act or ref command period trc 48.000 - 49. 125 (49.125) 5,11 - ns act to pre command period tras 36.000 9*trefi 36.000 9*trefi ns cl=5 cwl=5 tck( avg) 2.500 3.300 reserved reserved ns cwl=6 tck(avg) reserved reserved reserved reserved ns cwl=7 tck(avg) reserved reserved reserved reserved ns cl=6 cwl=5 tck(avg) 2.500 3.300 2.500 3.300 ns cwl=6 tck(avg) reserved reserved reserved reserved ns cwl=7 tck(avg) reserved reserved reserved reserved ns cl=7 cwl=5 tck(avg) reserved reserved reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 * <2.5 * ns cwl=7 tck(avg) reserved reserved reserved reserved ns cl=8 cwl=5 tck(avg) reserved reser ved reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns cwl=7 tck(avg) 1.500 <1.875 reserved reserved ns cl=9 cwl=5 tck(avg) reserved reserved reserved reserved ns cwl=6 tck(avg) reserved reserved reserved reserved ns cwl=7 tck(avg) 1. 500 <1.875 1.500 <1.875 ns cl=10 cwl=5 tck(avg) reserved reserved reserved reserved ns cwl=6 tck(avg) reserved reserved reserved reserved ns cwl=7 tck(avg) 1.500 * <1.875 * 1.500 * <1.875 * ns supported cl settings 5,6,7,8,9 5, 6,7,8,9 nck supported cw l settings 5,6,7 5,6,7 nck *: optional
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 15 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ddr3 - 1 600 mhz speed bin ddr3 - 1 600 unit cl - nrcd - nrp 1 1 - 1 1 - 1 1 ( - d i ) parameter symbol min max internal read command to first data taa 13.75 (13.125) 5,11 20.000 ns act to internal read or write delay time trcd 1 3.75 (13.125) 5,11 - ns pre command period trp 13.75 (13.125) 5,11 - ns act to act or ref command period trc 4 8.75 (48.125) 5,11 - ns act to pre command period tras 3 5 .000 9*trefi ns cl=5 cwl=5 tck(avg) 3.000 3.300 ns cwl=6 tck(avg) reserved reserved n s cwl=7 tck(avg) reserved reserved ns cl=6 cwl=5 tck(avg) 2.500 3.300 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=7 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 * <2.5 * ns cwl=7 tck(avg) reserved r eserved ns cl=8 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cl=9 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 <1.875 ns cl=10 cwl=5 tck(av g) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.500 * <1.875 * ns cl=1 1 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cwl= 8 tck(avg) 1. 25* <1. 5* ns support ed cl settings 5, 6, ( 7 ) ,8, ( 9 ) ,10 , 11 nck supported cwl settings 5,6,7 ,8 nck *: optional
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 16 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ac timing specifications for ddr 3 sdram devices used on module (1066mhz) parameter symbol ddr3 - 1 066 units notes min. max. clock timing minimum clock cy cle time (dll off mode) tck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min max.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 90 90 ps clock period jitter du ring dll locking period jit(per, lck) - 80 80 ps cycle to cycle period jitter tjit(cc) 180 180 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 160 160 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 132 132 ps cumulative error across 3 cycles terr(3per) - 157 157 ps cumulative error across 4 cycles terr(4per) - 175 175 ps cumulative error across 5 cycles terr(5per) - 188 188 ps cumulative error across 6 cycles terr(6per) - 200 200 ps cumulative error across 7 cycles terr(7per) - 209 209 ps cumulative error across 8 cycles terr(8per) - 217 217 ps cumulative error across 9 cycles terr(9per) - 224 224 ps cumulative error across 10 cycles terr(10per) - 231 231 ps cumulative error across 11 cycles terr(11per) - 237 237 ps cumulative error across 12 cycles terr(12per) - 242 242 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 150 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 600 300 ps dq high impedance time from ck, ck# thz(dq) - 300 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 25 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 75 ps data hold time from dqs, dqs# referenced to vih( dc) / vil(dc) levels tdh(base) dc100 100 ps dq and dm input pulse width for each input tdipw 490 ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.38 - tck(avg) dqs, dqs# differential output low time tqsl 0.38 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck (avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 300 300 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 600 300 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 300 tck(avg) dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# fallin g edge setup time to ck, ck# rising edge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing dll locking time tdllk 512 - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 17 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. internal read command to precharge comma nd delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period fo r 1kb page size trrd max(4nck, 7.5ns) - active to active command period for 2kb page size trrd trrdmin.: max(4nck, 10ns) trrdmax.: four activate window for 1kb page size tfaw 37.5 - ns four activate window for 2kb page size tfaw 50 - ns com mand and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 125 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 200 - ps command and address setup time to ck, ck# referen ced to vih(ac) / vil(ac) levels tis(base) ac150 125+150 - ps control and address input pulse width for each input tipw 780 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or po wer - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp tx pmin.: max(3nck, 7.5ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5.625 ns) tckemax.: - command p ass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea comman d to power down entry tprpden tprpdenmin.: 1 tprpdenmax.: - nck timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 18 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tc k(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command t o power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 300 300 ps rtt_nom and rtt_wr turn - off time from o dtloff reference taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is pr ogrammed twldqsen 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 245 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 245 - ps write leveling output d elay twlo 0 9 ns write leveling output error twloe 0 2 ns
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 19 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ac timing specifications for ddr3 sdram devices used on module (1333mhz) parameter symbol ddr3 - 1333 units notes min. max. clock timing minimum clock cycle time (dll off mode) t ck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit (per)min max.: tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 80 80 ps clock period jitter during dll locking period j it(per, lck) - 70 70 ps cycle to cycle period jitter tjit(cc) 160 160 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 140 140 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 118 118 ps cumulative error across 3 cycles terr(3per) - 140 140 ps cumulative error across 4 cycles terr(4per) - 155 155 ps cumulative error across 5 cycles terr(5per) - 168 168 ps cumulative error across 6 cycles terr(6per) - 177 177 ps cumulative error a cross 7 cycles terr(7per) - 186 186 ps cumulative error across 8 cycles terr(8per) - 193 193 ps cumulative error across 9 cycles terr(9per) - 200 200 ps cumulative error across 10 cycles terr(10per) - 205 205 ps cumulative error across 11 cycles te rr(11per) - 210 210 ps cumulative error across 12 cycles terr(12per) - 215 215 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps dat a timing dqs, dqs# to dq skew, per group, per access tdqsq - 125 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 500 250 ps dq high impedance time from ck, ck# thz(dq) - 250 ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 - ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 30 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(b ase) dc100 65 ps dq and dm input pulse width for each input tdipw 400 - ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# dif ferential output high time tqsh 0.4 - tck(avg) dqs, dqs# differential output low time tqsl 0.4 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising ed ge output access time from rising ck, ck# tdqsck - 255 255 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 500 250 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 250 tck(avg) dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.25 0.25 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - tck(avg) command and address timing dll locking time tdllk 512 - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 20 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. internal read command to precharge command delay trtp trtpmin.: max( 4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 nck auto precharge writ e recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd trrdmin. : max(4nck, 6ns) trrdmax.: active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 0 ns four activate window for 2kb page size tfaw 45 0 ns command and addre ss setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 65 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 140 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 65+125 - ps control and address input pulse width for each input tipw 620 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal operation short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not req uiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmi n.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (p dx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6 ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck ,5.625 ns) tckemax.: - command pass disable del ay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 tprpdenmax.: - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 21 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(a vg)) twrpdenmax.: - nck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpden max.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down en try tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 250 250 ps rtt_nom and rtt_wr turn - off time from odtloff referenc e taof 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqse n 25 - nck write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 195 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 195 - ps write leveling output delay twlo 0 9 ns write leveling output error twloe 0 2 ns
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 22 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. ac timing specifications for ddr3 sdram devices used on module ( 1600 mhz) parameter symbol ddr3 - 1600 units notes min. max. clock timing minimum clock cycle time (dll off mode) tck (dll_off) 8 - ns average clock period tck(avg) refer to "standard speed bins) ps average high pulse width tch(avg) 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min max.: t ck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - tck(avg) clock period jitter jit(per) - 7 0 7 0 ps clock period jitter during dll locking period jit(per, lck) - 6 0 6 0 ps cycle to cycle period jitter tjit(cc) 140 1 4 0 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 1 2 0 1 2 0 ps duty cycle jitter tjit(duty) - - ps cumulative error across 2 cycles terr(2per) - 103 103 ps cumulative err or across 3 cycles terr(3per) - 1 22 122 ps cumulative error across 4 cycles terr(4per) - 1 36 1 36 ps cumulative error across 5 cycles terr(5per) - 1 47 1 47 ps cumulative error across 6 cycles terr(6per) - 1 55 1 55 ps cumulative error across 7 cycles t err(7per) - 1 63 1 63 ps cumulative error across 8 cycles terr(8per) - 1 69 1 69 ps cumulative error across 9 cycles terr(9per) - 175 175 ps cumulative error across 10 cycles terr(10per) - 180 180 ps cumulative error across 11 cycles terr(11per) - 184 1 84 ps cumulative error across 12 cycles terr(12per) - 188 188 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max ps data timing dqs, dqs# to dq skew, per group, per access tdqsq - 100 ps dq output hold time from dqs, dqs# tqh 0.38 - tck(avg) dq low - impedance time from ck, ck# tlz(dq) - 450 2 2 5 ps dq high impedance time from ck, ck# thz(dq) - 2 2 5 ps data setup time to dq s, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 - ps data setup time to dqs, dqs# referenced to vih(ac) / vil(ac) levels tds( base) ac150 10 ps data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 4 5 p s dq and dm input pulse width for each input tdipw 36 0 - ps data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 tck(avg) dqs, dqs# differential read postamble trpst 0.3 note 11 tck(avg) dqs, dqs# differential output high time tqsh 0.4 - tck(avg) dqs, dqs# differential output low time tqsl 0.4 - tck(avg) dqs, dqs# differential write preamble twpre 0.9 - tck(avg) dqs, dqs# differential write postamble twpst 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck - 255 255 tck(avg) dqs and dqs# low - impedance time (referenced from rl - 1) tlz(dqs) - 450 2 2 5 tck(avg) dqs and dqs# high - impedance time (referenced from rl + bl/2) thz(dqs) - 225 tck(avg) dqs, dqs# differential in put low pulse width tdqsl 0.45 0.55 tck(avg) dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 tck(avg) dqs, dqs# rising edge to ck, ck# rising edge tdqss - 0.2 7 0.2 7 tck(avg) dqs, dqs# falling edge setup time to ck, ck# rising edge tds s 0. 18 - tck(avg) dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0. 18 - tck(avg) command and address timing dll locking time tdllk 512 - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 23 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) t rtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - ns mode register set command cycle time tmrd 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd pre command period trp act to act or ref command period trc cas# to cas# command delay tccd 4 nck auto precharge write recovery + p recharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi - purpose register recovery time tmprr 1 - nck active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd trrdmin.: max(4nck, 6n s) trrdmax.: active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 - ns four activate window for 2kb page size tfaw 4 0 - ns command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 45 - ps command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 1 2 0 - ps command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) leve ls tis(base) ac150 170 - ps control and address input pulse width for each input tipw 560 - ps calibration timing power - up and reset calibration time tzqinit 512 - nck normal operation full calibration time tzqoper 256 - nck normal ope ration short calibration time tzqcs 64 - nck reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked d ll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) txsdllmax.: - nck minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power - down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power - down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6 ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck ,5 ns) tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 tcpdedmin.: - nck power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 tactpdenmax.: - nck timing of pre or prea command to power down entry tprpden tprpde nmin.: 1 tprpdenmax.: - nck
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 24 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 trdpdenmax.: - nck timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) twrpdenmax.: - n ck timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 twrapdenmax.: - nck timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 twrapdenmax.: - nck timing of ref command to power down entry trefpden trefpdenmin.: 1 trefpdenmax.: - nck timing of mrs command to power down entry tmrspden tmrspden min.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 odth4max.: - nck odt high time with write command and bl8 odth8 odth8min.: 6 odth8max.: - nck asynchronous rtt turn - on delay (power - down with dll frozen) taonpd 2 8.5 ns asynchronous rtt turn - off delay (power - down with dll frozen) taofpd 2 8.5 ns rtt turn - on taon - 2 25 2 25 ps rtt_nom and rtt_wr turn - off time from odtloff reference taof 0.3 0.7 tck(av g) rtt dynamic change skew tadc 0.3 0.7 tck(avg) write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - nck write l eveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 1 6 5 - ps write leveling hold time from rising dqs, dqs# crossing to rising ck, ck# crossing twlh 1 6 5 - ps write leveling output delay twlo 0 7.5 ns write leveling output error twloe 0 2 ns
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 25 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. package dimensions [1g b C 1 r ank, 128 mx16 ddr 3 sdrams ] note: device position and scale are only for reference. d e t a i l b d e t a i l a 2 . 0 ( 0 . 0 7 9 ) 6 . 0 ( 0 . 2 3 6 ) 1 2 0 3 6 7 . 6 0 + / - 0 . 1 5 ( 2 . 6 6 1 + / - 0 . 0 0 6 ) 2 0 . 0 ( 0 . 7 8 7 ) 3 0 . 0 + / - 0 . 1 5 ( 1 . 1 8 1 + / - 0 . 0 0 6 ) 6 3 . 6 0 ( 2 . 5 0 4 ) 2 x o 1 . 8 0 ( 0 . 0 7 1 ) 2 1 . 0 ( 0 . 8 2 7 ) 3 9 . 0 ( 1 . 5 3 5 ) 1 . 3 5 ( 0 . 0 5 3 ) 4 . 0 ( 0 . 1 5 7 ) 1 . 0 0 + / - 0 . 1 2 . 7 m a x . ( 0 . 1 5 0 m a x . ) 2 x 4 . 0 + / - 0 . 1 ( 0 . 1 5 7 + / - 0 . 0 0 4 ) 3 . 0 ( 0 . 1 1 8 ) 1 . 6 5 ( 0 . 0 6 5 ) 1 . 0 ( 0 . 0 3 9 ) 0 . 6 ( 0 . 0 2 4 ) 0 . 4 5 + / - 0 . 0 3 ( 0 . 0 1 8 + / - 0 . 0 0 1 ) 2 . 5 5 ( 0 . 1 0 0 ) 0 . 2 5 m a x . ( 0 . 0 1 0 m a x . ) d e t a i l a d e t a i l b u n i t s : m i l l i m e t e r s ( i n c h e s )
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 26 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. package dimensions [2g b C 1 r ank, 256 mx 8 dd r 3 sdrams ] note: device position and scale are only for reference. d e t a i l b d e t a i l a 2 . 0 ( 0 . 0 7 9 ) 6 . 0 ( 0 . 2 3 6 ) 1 2 0 3 6 7 . 6 0 + / - 0 . 1 5 ( 2 . 6 6 1 + / - 0 . 0 0 6 ) 2 0 . 0 ( 0 . 7 8 7 ) 3 0 . 0 + / - 0 . 1 5 ( 1 . 1 8 1 + / - 0 . 0 0 6 ) 6 3 . 6 0 ( 2 . 5 0 4 ) 2 x o 1 . 8 0 ( 0 . 0 7 1 ) 2 1 . 0 ( 0 . 8 2 7 ) 3 9 . 0 ( 1 . 5 3 5 ) 1 . 3 5 ( 0 . 0 5 3 ) 4 . 0 ( 0 . 1 5 7 ) 1 . 0 0 + / - 0 . 1 3 . 8 m a x . ( 0 . 1 5 0 m a x . ) 2 x 4 . 0 + / - 0 . 1 ( 0 . 1 5 7 + / - 0 . 0 0 4 ) 3 . 0 ( 0 . 1 1 8 ) 1 . 6 5 ( 0 . 0 6 5 ) 1 . 0 ( 0 . 0 3 9 ) 0 . 6 ( 0 . 0 2 4 ) 0 . 4 5 + / - 0 . 0 3 ( 0 . 0 1 8 + / - 0 . 0 0 1 ) 2 . 5 5 ( 0 . 1 0 0 ) 0 . 2 5 m a x . ( 0 . 0 1 0 m a x . ) d e t a i l a d e t a i l b u n i t s : m i l l i m e t e r s ( i n c h e s )
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 27 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. package dimensions [4g b C 2 r ank s , 256 mx 8 ddr 3 sdrams ] note: device position and scale are only for reference. d e t a i l b d e t a i l a 2 . 0 ( 0 . 0 7 9 ) 6 . 0 ( 0 . 2 3 6 ) 1 2 0 3 6 7 . 6 0 + / - 0 . 1 5 ( 2 . 6 6 1 + / - 0 . 0 0 6 ) 2 0 . 0 ( 0 . 7 8 7 ) 3 0 . 0 + / - 0 . 1 5 ( 1 . 1 8 1 + / - 0 . 0 0 6 ) 6 3 . 6 0 ( 2 . 5 0 4 ) 2 x o 1 . 8 0 ( 0 . 0 7 1 ) 2 1 . 0 ( 0 . 8 2 7 ) 3 9 . 0 ( 1 . 5 3 5 ) 1 . 3 5 ( 0 . 0 5 3 ) 4 . 0 ( 0 . 1 5 7 ) 1 . 0 0 + / - 0 . 1 3 . 8 m a x . ( 0 . 1 5 0 m a x . ) 2 x 4 . 0 + / - 0 . 1 ( 0 . 1 5 7 + / - 0 . 0 0 4 ) 3 . 0 ( 0 . 1 1 8 ) 1 . 6 5 ( 0 . 0 6 5 ) 1 . 0 ( 0 . 0 3 9 ) 0 . 6 ( 0 . 0 2 4 ) 0 . 4 5 + / - 0 . 0 3 ( 0 . 0 1 8 + / - 0 . 0 0 1 ) 2 . 5 5 ( 0 . 1 0 0 ) 0 . 2 5 m a x . ( 0 . 0 1 0 m a x . ) d e t a i l a d e t a i l b u n i t s : m i l l i m e t e r s ( i n c h e s )
m2s1g64cbh4b5p / m2s2g64cb88b5n / M2S4G64CB8HB5N 1g b: 128m x 64 / 2g b: 256m x 64 / 4 g b: 512 m x 64 pc3 - 85 00 / pc3 - 10600 / pc3 - 12800 unbuffered ddr 3 so - dimm rev 1. 2 28 0 9 /20 10 ? nanya technology corporation nanya res erves the right to change products and specifications without notice. revision log rev date modification 0.1 01/2010 preliminary release 0.5 05/2010 preliminary release 2 1.0 0 5 /2010 official release 1.1 07/2010 version updated, added 1gb product. 1.2 09/2010 version updated, added 1600mhz product and cl=5 spec . nanya t echnology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886 - 3 - 328 - 1688 please visit our home page for more information: www.elixir - memory.com printed in taiwan ? 20 10

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